Title:
分周回路及び半導体集積回路
Document Type and Number:
Japanese Patent JP6684218
Kind Code:
B2
Abstract:
A plurality of latch circuits driven at rising of a clock signal and a plurality of latch circuits driven at falling of the clock signal are alternately connected, and generation circuit generates a plurality of frequency divided clock signals with different phases based on combinations of levels of outputs of the plurality of latch circuits.
Inventors:
Tetsuro Tamura
Application Number:
JP2016543531A
Publication Date:
April 22, 2020
Filing Date:
August 20, 2014
Export Citation:
Assignee:
Socionext Inc.
International Classes:
H03K27/00; H03K23/54
Domestic Patent References:
| JP61206313A | ||||
| JP5484471A | ||||
| JP62192097A | ||||
| JP4212521A |
Attorney, Agent or Firm:
Takayoshi Kokubun