PURPOSE: To obtain a high-speed frequency dividing circuit whose highest operation frequency is determined by the delay time of one stage of an inverter by composing the circuit of an inverter circuit, 1st and 2nd source followers, and 1st and 2nd transmission gates.

CONSTITUTION: The inverter circuit 3 consists of FETs TRQ1 and TRQ2, etc., the 1st source follower circuit 4 consists of TRs Q4, Q5, Q6, Q7, etc., and the 2nd source follower circuit 5 consists of TRs Q10, Q11, Q12, and Q13. The 1st and 2nd gate circuit 5 consist of TRs Q8 and Q9, and TRs Q14 and Q15. In this circuit, mutually opposite-phase AC inputs C' and the inverse of C' are applied through the transmission gate circuit 5 and then they are applied to the inverter circuit 3. Then the circuit is switched through the source follower circuit 4 and 1/2 frequency division outputs are obtained at outputs Q' and Q'.