Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
FREQUENCY DIVISION CIRCUIT
Document Type and Number:
Japanese Patent JPH11225064
Kind Code:
A
Abstract:

To provide a frequency division circuit having a frequency division ratio of an optional fraction.

A counter section 10 is operated, based on a control signal CS1 when a count CNT3 of a counter section 40 is 0-2, and applies 1/5 frequency division to an input signal IN to output a frequency division signal S1. A counter 41 counts up with the frequency division signal S1 given via an OR 30 and when the count CNT3 reaches 3 or 4, the counter section 10 is stopped, a counter section 20 is operated instead to apply 1/6 frequency division to the input signal IN and to output a frequency division signal S2. The frequency division signals S1, S2 are outputted via an OR 30 as an output signal OUT. A desired frequency division ratio (P+Q)/(M×P+N×Q) is obtained by selecting frequency division ratios 1/M, 1/N of the counter sections 10, 20 and output periods P, Q of control signals CS1, CS2 of the counter section 40, where, N are integers being 2 or over and P, Q are integers being 1 or over.


Inventors:
YAMAUCHI SHIGEKI
Application Number:
JP2499298A
Publication Date:
August 17, 1999
Filing Date:
February 06, 1998
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
OKI ELECTRIC IND CO LTD
International Classes:
H03K21/00; G08C19/00; G08C19/18; H03K23/68; (IPC1-7): H03K21/00; H03K23/68
Attorney, Agent or Firm:
Kakimoto Kyosei



 
Previous Patent: PARTIALLY REWRITABLE PLD

Next Patent: SIGNAL GENERATOR