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Title:
FREQUENCY SCANNING FAST TRAVERSE METHOD
Document Type and Number:
Japanese Patent JPS60158714
Kind Code:
A
Abstract:

PURPOSE: To improve the reliability in a high-speed scanning mode by giving m-multiple to the reference frequency of phase synchronization and also m-division to the division ratio of a program divider.

CONSTITUTION: The reference frequency fr is set at m-fold f'r in a fast traverse mode of frequency scanning by giving m-division to the division ratio of a frequency divider 4' of a reference oscillator 3. A CPU2 supplies the division data 21 to a programmable divider 12 and also the division data 22 to the divider 4'. The CPU2 supplies usually the M-division and N-division data to the dividers 4' and 12 respectively. While in a high-speed scanning mode, the data 22 gives m-division to the division ratio of the divider 4' to change the frequency f'r to mfr. Then the data 21 gives m-division to the division ratio of the divider 12 to change the frequence f'v to mfv. For this purpose, a program is compiled for the CPU2. Thus it is possible to get rid of a factor for unstable actions including a changeover switch, etc. for a circuit. Then only the softward of the CPU carries out operations. This improves the reliability in the fast traverse mode of frequency scanning.


Inventors:
HASHIMOTO YOSHITERU
Application Number:
JP1476284A
Publication Date:
August 20, 1985
Filing Date:
January 30, 1984
Export Citation:
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Assignee:
YAESU MUSEN KK
International Classes:
H03J7/28; H03J1/00; (IPC1-7): H03J7/28
Domestic Patent References:
JPS58205323A1983-11-30



 
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