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Title:
FREQUENCY SYNCHRONIZATION LOOP CIRCUIT AND PHASE SYNCHRONIZATION LOOP CIRCUIT
Document Type and Number:
Japanese Patent JP2002271191
Kind Code:
A
Abstract:

To provide a PLL (FLL) circuit which uses a smaller circuit space, together with a measuring circuit having specific parameters, and can be manufactured with high cost-effectiveness.

This PLL (FLL) circuit comprises a phase (frequency) comparator 6, which controls output signals so as to make a phase (frequency) error small by comparing the phase relation (frequency) of the output signals of a follow-up oscillator 3 with that of the output signals of a reference oscillator 2, when the output signals which characterize a phase (frequency) shift are supplied to the oscillator 3; the controllable oscillator 3 in which the phase relation (frequency) of signals is affected by external parameters, the reference oscillator 2 whose signals have a constant phase relation (frequency); and an external parameter monitoring device 10 which receives signals representing the output signals, which characterize a phase (frequency) shift and converts the signals into a measured value, that represents the actual value of the external parameters.


Inventors:
DIEWALD HORST
Application Number:
JP2002038092A
Publication Date:
September 20, 2002
Filing Date:
February 15, 2002
Export Citation:
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Assignee:
TEXAS INSTRUMENTS DEUTSCHLAND
International Classes:
G01K7/32; H03L7/08; H03L7/06; H03L7/18; H03L7/099; (IPC1-7): H03L7/08
Attorney, Agent or Firm:
Akira Asamura (3 outside)