PURPOSE: To eliminate ripples of an output voltage without losing the response of an F/V converter.

CONSTITUTION: A sample-and-hold circuit 2 is connected to an F/V converter 1 and an output voltage with a ripple of the F/V converter is integrated by an integration device 31 from a rising of an input pulse, a comparator 32 compares the voltage with a reference voltage set by a resistor R4 to detect a phase shifting of nearly 270° of the ripple, a rising detector 33 provides an output of a sample signal to the circuit 2 to sample and hold the output voltage of the F/V converter. The ripple voltage at a phase of nearly 270° is an ideal output voltage independently of the frequency of the input pulse. Since the integration is started at every rising of the input pulse, the detector 41 detects the rising of the input pulse to set a flip-flop(FF) 45. Then a switch T1 connecting to an integration capacitor C3 is open to start integration, and a detector 43 detects a trailing of the sample signal to reset the FF 45 and to close the switch T1 and then the integration is stopped.