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Patent Searching and Data


Title:
GALLIUM ARSENIDE SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS6236918
Kind Code:
A
Abstract:

PURPOSE: To inserr a lvel conversion circuit between 2-stage of series connection E/D inverter circuits so as to descend the low level into a negative potential.

CONSTITUTION: A logic signal from a node 10 is inverted by an inverter and its level is subjected to level conversion by a level conversion circuit comprising a normally-off metal-semiconductor FET (MESFET) 5, a Schottky diode 7 and a normally-on MESFET 2. The high level to a level of a node 11 is selected equal to the high level of the internal logic amplitude of an E/D direct coupled FET logic circuit and the low level is brought into a common potential by selecting properly the circuit constant of the conversion circuit and the negative power supply of a node 13. In this case, the normally-off MESFET 6 is turned off completely to a low level of the node 13 regardless of the variation in the thereshold voltage and the inverter comprising the normally-on MESFET 3 and the normally-off MESFET 6 gives always normal inverting operation.


Inventors:
MAKINO HIROYUKI
TAKANO SATOSHI
Application Number:
JP17633485A
Publication Date:
February 17, 1987
Filing Date:
August 09, 1985
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L21/8222; H01L27/082; H03K19/0952; (IPC1-7): H01L27/08; H03K19/094
Attorney, Agent or Firm:
Kenichi Hayase