Title:
局所酸化物を有するゲートオールアラウンドデバイスアーキテクチャ
Document Type and Number:
Japanese Patent JP7023284
Kind Code:
B2
Abstract:
A system and method for fabricating non-planar devices while managing short channel and heating effects are described. A semiconductor device fabrication process includes forming a non-planar device where the body of the device is insulated from the silicon substrate, but the source and drain regions are not insulated from the silicon substrate. The process builds a local silicon on insulator (SOI) while not insulating area around the source and drain regions from the silicon substrate. A trench is etched a length at least that of a channel length of the device while being bounded by a site for a source region and a site for a drain region. The trench is filled with relatively thick layers to form the local SOI. When nanowires of a gate are residing on top of the layer-filled trench, a second trench is etched into the top layer for depositing gate metal in the second trench.
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Inventors:
Richard Tee. Schultz
Application Number:
JP2019537029A
Publication Date:
February 21, 2022
Filing Date:
September 19, 2017
Export Citation:
Assignee:
ADVANCED MICRO DEVICES INCORPORATED
International Classes:
H01L21/336; H01L29/78; H01L29/786
Domestic Patent References:
| JP2014505995A | ||||
| JP2012518269A | ||||
| JP2011066151A | ||||
| JP2006210854A | ||||
| JP2015516679A | ||||
| JP2013527607A |
Foreign References:
| US20120007051 | ||||
| US20150295036 |
Attorney, Agent or Firm:
Yuji Hayakawa
Ryota Sano
Keisuke Murasame
Ryota Sano
Keisuke Murasame