GATE ARRAY COMPATIBLE WITH PLURALITY OF POWER SUPPLIES

Title:

GATE ARRAY COMPATIBLE WITH PLURALITY OF POWER SUPPLIES

Document Type and Number:

Japanese Patent JPH07130969

Kind Code:

A

Abstract:

PURPOSE: To suppress a drop in the reliability of an element such as a transistor or the like due to its damage or the like by an applied voltage when a high- voltage power supply is used and to enhance its operating speed when a low- voltage power supply is used.

CONSTITUTION: An inverter gate which is used as an input buffer is formed of a P-channel MOS transistor Tpt1 and an N-channel MOS transistor Tn1. AP-channel M0S transistor Tpt1 is connected in series with the P-channel MOS transistor Tp1, when a high-voltage power supply at 5.0V is supplied, and it controls a voltage which is applied to an element. On the other hand, the P- channel MOS transistor Tpt1 is connected in parallel with the P-channel MOS transistor Tp1 when a low-voltage power supply at 3.3V or the like is supplied, and it helps a load driving operation in a next stage.

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Inventors:

KEIDA HISAYA

Application Number:

JP15875593A

Publication Date:

May 19, 1995

Filing Date:

June 29, 1993

Export Citation:

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Assignee:

KAWASAKI STEEL CO

International Classes:

H01L27/118; G11C11/401; H01L21/82; (IPC1-7): H01L27/118

Attorney, Agent or Firm:

Satoshi Takaya (2 outside)

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