To provide a generating circuit for pulse width modulation (PWM) signal that can faithfully generate PWM signals of the duty in a prescribed period, based on set data over the entire period.

In the PWM signal generating circuit, provided with a ring counter 5, a latch section which holds desired bit data used for discriminating the validity/invalidity of the output of an active pulse continuously going round on the ring counter 5, is constituted of an 8-bit prestage register 4 and two poststage registers 12 and 13 which respectively latch the upper-and lower-order 4-bits of the register 4. In the prestage register 4 and poststage registers 12 and 13, data updating is performed in a period which is eight times as long as that of a ultrahigh-speed clock inputted to the ring counter 5 and with clocks of different phases.