PURPOSE: To recude a circuit scale by providing an area based on a maximum extension quantity to a storage means, and specifying an address by an address output means based on a set delay quantity.

CONSTITUTION: A digital video signal is inputted to an input terminal 11, and this input video signal is applied to a serial/parallel converting circuit (SP converting circuit) 31. The SP converting circuit 31 converts the serial video signal into a 2n bit parallel signal and applies to a memory device 32. The memory device 32 has the area of 2n×2m (=the maximum delay quantity), and each area is constituted by the same number of bit as an input signal. Parallel data of 2n bit read out from the memory 32 are applied to parallel/ serial converting circuits (PS converting circuit) C1-Cn, and the respective PS converting circuits C1-Cn converts the inputted parallel data into serial data, and outputs to variable delay circuits T1-Tn respectively. Thus, it is possible to reduce a number of steps of delay, and to reduce the circuit scale.