Title:
GOLD SYSTEM GENERATING CIRCUIT
Document Type and Number:
Japanese Patent JPH11259276
Kind Code:
A
Abstract:
To provide a circuit for quickly generating a GOLD system without quickening any clock.
The exclusive logical sum of M series codes outputted from two M series generating circuits 11(11A-1-11A-K, 11B-1-11B-K) for simultaneously generating plural M series codes is received by an exclusive logical sum circuit 2 (2-1-2-K) so that plural GOLD series codes can be generated in parallel. Then, the parallel GOLD series codes are converted into serial codes by a muliplexer 3, and outputted.
Inventors:
HASEGAWA NORIAKI
TAKADA MASATOSHI
TAKADA MASATOSHI
Application Number:
JP5929898A
Publication Date:
September 24, 1999
Filing Date:
March 11, 1998
Export Citation:
Assignee:
KOKUSAI ELECTRIC CO LTD
International Classes:
G06F7/58; G06F17/10; H03K3/84; H04J13/00; H04J13/10; (IPC1-7): G06F7/58; G06F17/10; H03K3/84
Attorney, Agent or Firm:
Nobuhiro Funatsu (1 outside)
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