To provide a gray code counter, where the number of delay flip-flops is reduced and current consumption is reduced.

The gray code counter has four DFFs 11, 12, 13, 14 for holding respective bits Q3, Q2, Q1, Q0 of a gray code, a reference bit creation circuit 30 for creating a reference bit Qb, and a decode circuit for decoding Qb, Q0, Q1. The four DFFs 11, 12, 13, 14 are reset by a reset signal RESET to hold and delay data in synchronism with the reference clock CLK. More specifically, the DFFs 11, 12, 13, 14 fetch and hold data from a data input terminal D in synchronism with the rising of the reference clock CLK, and then output it from a data output terminal Q in synchronism with the rising of the next reference clock CLK.