Title:
MANUFACTURE OF SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JP3241242
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To make it possible to facilitate the process of a storage electrode by forming an interlayer insulating film on an interconnection layer, depositing a conductive electrode material on the insulating film, processing conductive electrode material to simultaneously form the interconnection layers of the charge storage electrode of the cell and out of the cell region.
SOLUTION: The method for manufacturing a semiconductor memory comprises the steps of depositing an oxide film 14 as an interlayer insulating film, then opening the storage electrode connecting hole 8c of the cell and the connecting hole 9c of a peripheral circuit part by using lithographic method and etching technology, further forming a groove 15 for the storage electrode of the cell and the interconnection groove 16 of the peripheral circuit by using the lithographic method and the etching technology, then depositing the conductive electrode material, embedding the holes 8c, 9c, 10, the groove 15 for the electrode and the groove 16 for the circuit, and simultaneously forming the interconnection layer 19 of the electrode 18 and the circuit.
Inventors:
Akira Sudo
Shizuo Sawada
Shizuo Sawada
Application Number:
JP24411495A
Publication Date:
December 25, 2001
Filing Date:
September 22, 1995
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L27/04; H01L21/822; H01L21/8242; H01L27/108; (IPC1-7): H01L27/108; H01L21/822; H01L21/8242; H01L27/04
Domestic Patent References:
| JP7106437A | ||||
| JP945878A | ||||
| JP8204012A |
Attorney, Agent or Firm:
Takehiko Suzue
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