To accelerate the CPU switching of a high-speed and good debugging hardware/software co-verification system.

The hardware/software co-verification system comprises a source transfer control part 15 for monitoring memory write access to a source memory area for a circuit to be verified and storing address numbers of addresses of changed data in the memory area, a source data transfer part for, at mode switching, extracting the address numbers stored by the source transfer control part 15 and the data in the memory area represented by the address numbers and transferring the addresses and data, and a destination data transfer part 17 for, at mode switching, receiving and storing the address numbers and data transferred from the source data transfer part 16 and writing the data to addresses of a destination memory area corresponding to the stored addresses.

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