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Patent Searching and Data


Title:
HIDING SELECTION DEVICE AND ITS METHOD
Document Type and Number:
Japanese Patent JPH1079044
Kind Code:
A
Abstract:

To improve a graphics displaying speed by executing the hiding selection of a primitive.

A depth comparing circuit 33 inputting the primitive to express from a central processor compares the input depth value of each address in this primitive with the present depth value of a pixel expressed by a corresponding address. A result signal provided with a first logical value when an inputted depth value is visible but provided with a second logical value when the inputted depth value is hidden by the expressed pixel is generated. These logical values are latched to generate first and second logical level signals. When a first logical level is not latched, all the primitives in the group are hidden by primitives expressed before. Thus, the storage of a depth value to a depth buffer or the storage of a color value to a color buffer a is executed concerning a belonging pixel.


Inventors:
OLSEN DANIEL M
SCOTT NOEL D
CASEY ROBERT J
Application Number:
JP17606297A
Publication Date:
March 24, 1998
Filing Date:
July 01, 1997
Export Citation:
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Assignee:
HEWLETT PACKARD CO
International Classes:
G06T15/40; (IPC1-7): G06T15/40
Attorney, Agent or Firm:
Hideo Ueno