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Patent Searching and Data


Title:
HIGH DEFINITION TELEVISION RECEIVER
Document Type and Number:
Japanese Patent JPH03166886
Kind Code:
A
Abstract:

PURPOSE: To prevent deterioration in the audio and video signal by controlling a sample adjustment circuit with an interpolation signal outputted from an error correction circuit when an error is caused in the audio signal.

CONSTITUTION: An output of an A/D converter circuit 11 is subjected to inverse conversion with respect to conversion such as band compression implemented by the sender side. A frame pulse detection circuit detects a frame pulse and a timing generating circuit 17 generates a timing pulse of the circuit 12. A phase comparator circuit 14 outputs a phase error of a horizontal synchronizing signal. A voice signal is outputted by an error correction circuit 18 of a voice demodulation circuit when the error correction is disabled. An interpolation signal is inputted to a resample adjustment circuit 10, and an adder circuit 19 outputting a data adjusting re-sample adds an output of a phase comparator 14 and an output of the resample adjustment circuit 10. The output of the adder circuit 19 is integrated by an integration circuit 15 to absorb a sudden change. An output signal of the integration circuit 15 controls the oscillator of a clock generating circuit 16, a frequency divider circuit divides the frequency of the signal to generate a clock for the A/D converter and the digital circuit.


Inventors:
MIYOSHI TOSHIHIRO
OKUMURA NAOJI
Application Number:
JP30700389A
Publication Date:
July 18, 1991
Filing Date:
November 27, 1989
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H04N19/85; H04N7/00; H04N7/015; H04N19/00; H04N19/59; H04N19/65; (IPC1-7): H04N7/00; H04N7/13
Attorney, Agent or Firm:
Fumio Iwahashi (2 others)