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Title:
HIGH FREQUENCY 2 MULTIPLICATION CIRCUIT
Document Type and Number:
Japanese Patent JP2005236600
Kind Code:
A
Abstract:

To obtain a double wave efficiently by suppressing an output of a DC component when a signal of double frequency is generated from an original signal.

A high frequency signal source 103 represents the original signal for 2 multiplication, and generates a differential signal to output terminals 106 and 107. The signal from the signal source 103 is input to the bases of transistors Q1, Q3 and the bases of transistors Q2, Q4. Simultaneously, a differential input is applied to transistors Q5, Q6 through a capacitor. At this time, this circuit performs the same operation as a multiplier, and the double frequency of the original signal is generated as the differential output at the collector terminals of the transistors Q1, Q3 and Q2, Q4. At this time, the input original signal is not output according to the operation of the multiplier, but only the signal multiplied by the input signal is output merely.


Inventors:
ITO JUNJI
Application Number:
JP2004042426A
Publication Date:
September 02, 2005
Filing Date:
February 19, 2004
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H03F3/45; H03B19/14; H03D7/14; H03F3/34; H04N9/68; (IPC1-7): H03B19/14; H03D7/14; H03F3/34; H03F3/45
Attorney, Agent or Firm:
Fumio Iwahashi
Tomoyasu Sakaguchi
Hiroki Naito