To provide a high-speed arithmetic circuit, capable of accelerating a circuit operation when various types of calculations are carried out, as compared to prior art.

The high-speed arithmetic circuit comprises two MOS-transistor logic circuits 101 and 102 for obtaining two equal logic results. The logic circuit 101 inputs a first signal group of two inputs to its gate terminal and inputs a second signal group to a source terminal. The logic circuit 102 inputs a first signal group to its gate terminal and inputs a second signal group to its source terminal. The outputs of the logic circuits 101 and 102 are constituted so as to carry out wired OR operation by a wired-OR circuit 103.