Title:
HIGH-SPEED FOURIER TRANSFORM ARITHMETIC SYSTEM
Document Type and Number:
Japanese Patent JPS5846466
Kind Code:
A
Abstract:
PURPOSE:To shorten data transfer time by performing DFT (Discrete F.T.) between image memories without data transfer between a host machine, and putting the host machine in charge of only control over the memories. CONSTITUTION:In the figure, PM is a screen memory and (k) and (l), and Ki and li are one line data on its real part and imaginary part; and bits of respective pixel, and multipliers W, Wi, and -Wi are used as addresses by 256 look-up tables which correspond to respective input data on the 256 pixel to read the sum of them out of an LUT constituted as an ROM, thereby obtaining an output OUT. After two-divided outputs OUT2 and OUT2 are obtained, two- divided data of each line data is further divided into two, which are processed similarly. Data k' and k'', and l'1 and l'' are obtained from two-divided data (k) and (l) and those data k' and l', and k'' and l'' are processed similarly for transform (k'-k'') R'1, and (l'-l'') R'2. In this case R'1 is obtained by dividing R1 into two, and R'2 is obtained by dividing R2 into two; contents of k' and k'', and l' and l'' are those in outputs OUT2 and OUT'2.
Inventors:
SEKIYA TOMOTAKA
YAMAGUCHI HIDEJI
UEHARA KATSUNORI
YAMAGUCHI HIDEJI
UEHARA KATSUNORI
Application Number:
JP14533381A
Publication Date:
March 17, 1983
Filing Date:
September 14, 1981
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
G06F17/14; G06T1/20; (IPC1-7): G06F15/20
Attorney, Agent or Firm:
Minoru Aoyagi