Title:
HIGH SPEED INTEGRATED CIRCUIT TEST USING JTAG
Document Type and Number:
Japanese Patent JP3174617
Kind Code:
B2
Abstract:
PURPOSE: To test a digital processor at the maximum operation speed, by mounting an IC for high speed test which has a digital processor, on a joint tester action group(JTAG) test port, and transferring a test program.
CONSTITUTION: Programmable digital processors 21, 23, 24 and a P-ROM 22 constitute a digital processor. A test data register(TDR) 11 receives a test program via a serial test input port(TDI), and has (n) bit positions for transferring the test program, in the P-ROM 22. A test control register(JCOM) 10 executes block down loading of the test program on a TDR 11 under the control of a finite-state machine of JTAG and a command decoder, and makes the test program be received as continuous sequence of data words. The degital processor outputs the result of a processed program from a serial test output port TDO, via TDR 11.
Inventors:
Alan Joel Green Burger
Homayon Sam
Homayon Sam
Application Number:
JP10502992A
Publication Date:
June 11, 2001
Filing Date:
April 24, 1992
Export Citation:
Assignee:
AT&T CORP.
International Classes:
G06F11/267; H01L21/66; G01R31/28; (IPC1-7): G01R31/28
Domestic Patent References:
| JP396881A | ||||
| JP4263335A |
Attorney, Agent or Firm:
Masao Okabe (2 outside)
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