PURPOSE: To test a high-speed memory by adding a simple additional circuit to an existing memory tester.
CONSTITUTION: Test address information and test data generated by existing memory tester 10 are used to generate memory test cycles by an additional circuit (part other than tester 10) corresponding to one cycle of a test pattern generated by memory tester 10. The address information from memory tester 10 is written into address registers A and X and through address selecting circuit 1, data of register A or its inverted data, or data of register X or its inverted data is selected and set in address register 9 before being sent as address information to an equipment to be tested. Then, the test data from memory tester 10 is written in register T and selecting circuit 2 selects and sends the data of register T or its inverted data to shift register 3, so that it will be sent to the equipment to be tested.
NOZOE YUKIO
MORIOKA TSUNE
