Title:
HIGH-SPEED PULL-IN CONTROL CIRCUIT FOR CLOCK SUBORDINATE SYNCHRONIZATION DEVICE
Document Type and Number:
Japanese Patent JP2616701
Kind Code:
B2
Abstract:
PURPOSE: To shorten control at the time of starting a system since the time until the coincidence of frequency accuracy at the time of starting the system is long in the case of letting all clock supply devices inside a network be coincident to the frequency accuracy of clcoks outputted from the clock supply device of a master node in the subordinate synchronization system of a network synchronization system or the like.
CONSTITUTION: The 'advance' and 'lag' of the phases of input clock signals and output clock signals are detected in a differentiation circuit 9, the change point of the phase is detected, a controlled variable is changed and the control is performed. At the time, for the control at the normal time, masking is performed and the control is performed only by high-speed pull-in control. The controlled variable is reduced by 1/2 each in a selector 10 every time the change point is detected and the high-speed pull-in control is ended when the next change point is detected in the state of being ±1. In the control, since a difference is generated between frequency pull-in and phase pull-in, a correction amount is calculated in an integration circuit 12 and 1/2 of the respective controlled variables is turned to a reverse polarity and added as the correction amount.
Inventors:
Toshiya Nezu
Application Number:
JP14737994A
Publication Date:
June 04, 1997
Filing Date:
June 29, 1994
Export Citation:
Assignee:
NEC
International Classes:
H03L1/02; H03L3/00; H03L7/093; H03L7/10; H03L7/107; H03L7/12; H03L7/14; (IPC1-7): H03L7/12; H03L1/02; H03L7/093
Domestic Patent References:
| JP197017A |
Attorney, Agent or Firm:
Yanagi Kawa Shin
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