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Title:
HIGH WITHSTAND VOLTAGE TYPE SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS5756969
Kind Code:
A
Abstract:

PURPOSE: To increase the withstand voltage of a semiconductor device without deteriorating te characteristics of the device in which the junction surface is bevelled at the end face of an exposed substrate by forming the equal conductive type high density layer in a region extending at the depletion layer of the bevelled part, thereby reducing the bending of the depletion layer.

CONSTITUTION: A high density collector layer 3, a base layer 2 and an emitter layer 4 are formed, for example, on an n type high resistance wafer 10 by diffusing them from both main surfaces, as a transistor structure having high resistance collector region 1. Electrodes 4∼6 are formed on both main surfaces, the side surface of the wafer is positively bevelled, thereby increasing its withstand voltage. The deflected layer of the treated surface is etched and removed, n type impurity ions are injected in suitably amount at an adequate distance from the junction end 9a to the high resistance collector region 1 of the vebelled surface 10a, thereby forming a high density layer 11. In this manner, the shape 12a of the depletion layer of the collector side at the reverse bias time can be formed with less bending than the case that the injected layer 11 is not formed (as designated by chain line), and high withstand voltage can be formed without inreasing the thickness of the substrate 10.


Inventors:
TANAKA TOMOYUKI
Application Number:
JP13164080A
Publication Date:
April 05, 1982
Filing Date:
September 24, 1980
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L29/73; H01L21/312; H01L21/331; H01L29/06; H01L29/74; (IPC1-7): H01L21/322; H01L29/72
Domestic Patent References:
JP43009095A