Title:
HIGH WITHSTANDING VOLTAGE DRIVE CIRCUIT FOR CAPACITIVE LOAD
Document Type and Number:
Japanese Patent JP3181387
Kind Code:
B2
Abstract:
PURPOSE: To attain high speed and to allow the circuit to high-voltage drive by devising the circuit such that an equivalent 2-terminal element shows a constant voltage characteristic in the rising state for the high speed processing and shows a constant resistance in the falling state so as to divide a voltage applied to a drive element.
CONSTITUTION: In the rising state where a P-channel FET 21 is turned on and an N-channel FET 20 is turned off, a P-channel FET 22 is simultaneously turned on. Thus, an output resistance is only an ON-resistance of the FETs 21, 22 and a steep rising characteristic is obtained. In the case of a capacitive load, an output current is decreased, an output voltage is increased accordingly, a source-drain voltage of the FET 22 is decreased and when the voltage is less than a threshold voltage, the FET 22 is turned off. Then, the output voltage rises by a time constant depending on a resistance R2+R3 and a load capacitance. On the other hand, when the FET 21 is turned off, the FET 20 is turned on, since the FET 22 is turned off, the voltage applied to the FETs 21, 22 is divided by resistors R1, R2, R3 to allow the circuit to cope with high voltage drive.
Inventors:
Hiroyuki Kadowaki
Application Number:
JP20897492A
Publication Date:
July 03, 2001
Filing Date:
August 05, 1992
Export Citation:
Assignee:
Dai Nippon Printing Co.,Ltd.
International Classes:
H03K17/10; H03K17/687; (IPC1-7): H03K17/687
Domestic Patent References:
| JP491517A | ||||
| JP483420A | ||||
| JP4176211A |
Attorney, Agent or Firm:
Masanobu Ebikawa (7 others)
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