Title:
TIME-DIVISION MULTIPLEXED SIGNAL RECEIVING CIRCUIT
Document Type and Number:
Japanese Patent JP3180928
Kind Code:
B2
Abstract:
PURPOSE: To synchronize reception timing and decrease the scale of the circuit by supplying a signal indicating the head timing of a burst to a phase offset generating circuit when out-of-phase bursts are received from plural slave stations.
CONSTITUTION: A phase comparator 1 compares a reception demodulation output DEM-OUT with the reception timing RT and sends its output ε to a phase offset generating circuit 2. The circuit 2 presets the offset initial value from a phase offset storage circuit 3 in synchronism with a preset signal PR indicating the head timing of each burst from a burst timing generating circuit 8 and outputs the phase offset obtained by integrating the output ε of the comparator 1 for the initial value. Then, an adder 6 outputs the most significant digit bit of the remainder, obtained by dividing the addition result of a free-run reference frequency division phase obtained by dividing the frequency of a clock by N through an N-frequency-dividing counter 5 and the phase offset by N, as the reception timing. Consequently, the reception timing is synchronized to reduce the scale of the circuit.
Inventors:
Kenzo Urabe
Hitoshi Nobuta
Hitoshi Nobuta
Application Number:
JP13436792A
Publication Date:
July 03, 2001
Filing Date:
April 28, 1992
Export Citation:
Assignee:
Hitachi Kokusai Electric Co., Ltd.
International Classes:
H04J3/06; H04L7/10; (IPC1-7): H04J3/06; H04L7/10
Domestic Patent References:
| JP5757054A | ||||
| JP612435A | ||||
| JP2211731A |
Attorney, Agent or Firm:
Manabu Otsuka