PURPOSE: To suppress the parasitic oscillations at the time of a cut-off state by reducing the impedance of the gate side in the case of the positive gate bias and increasing the impedance with the inverse gate bias respectively for the application of the gate bias.

CONSTITUTION: At the time of energizing, the transistor TR 6 of a driving circuit is turned on and an SIT 11 is positively biased by a power supply VCC2 through the parallel circuit of the TR 6 and the resistors 20 and 10. In such conditions, the resistance of the SIT 11 is reduced by the parallel value of both resistors 20 and 10 at the gate side. Therefore the power voltage VCC2 is reduced and the loss of the driving circuit is also reduced. In an interruption state a TR 7 is turned on and a diode 21 is interrupted. Therefore the gate electrode of the SIT 11 is adversely biased through a resistor 10, the TR 7, and a negative power supply VCC. At this time, the resistor 10 is set at such a level where no parasitic oscillation occurs.