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Patent Searching and Data


Title:
連続時間積分器およびその積分期間を調整する方法
Document Type and Number:
Japanese Patent JP4777455
Kind Code:
B2
Abstract:
A hybrid tuning circuit is used consisting of a digital finite state machine and an analog tuning circuit to effectively keep the RC product of the continuous time integrator constant across process, temperature, supply, and sampling rate variations. Since the implementation is continuous, the tracking is more accurate than traditional techniques. Using a carefully chosen clocking scheme, the technique gets rid of inter-symbol interference in the feedback DAC. The technique does not use a reference frequency, thereby eliminating the need for a user to identify a reference frequency.

Inventors:
Nuian Chiem
Adams Robert W
Application Number:
JP2009284201A
Publication Date:
September 21, 2011
Filing Date:
December 15, 2009
Export Citation:
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Assignee:
Analog Devices Incorporated
International Classes:
H03M3/02; H03M3/04; H03H11/12
Foreign References:
EP0477694A1
Other References:
Bo Xia,Shauli Yan,Edgar Sanchez-Sinencio,AN AUTO-TUNING STRACTURE FOR CONTINUOUS TIME SIGMA-DELTA AD CONVERTER AND HIGH PRECISION FILTERS,Circuits and Systems, 2002 IEEE International Symposium on ,2002年,VOL.5,pp.V-593-V-596
Khiem Nguyen,Robert Adams,Karl Sweetland,Huaijin Chen,A 106-dB SNR Hybrid Oversampling Analog-to-Digital Converter for Digital Audio,Solid-State Circuits, IEEE Journal of,2005年12月,VOL.40,NO.12,p.2408-2415
WALDER J-P,A Low Power,Wide Dynamic Range Multi-Gain Signal Processor for the SNAP CCD.,2003 IEEE NUCLEAR SCIENCE SYMPOSIUM CONFERENCE RECORD.,米国,IEEE,2003年10月19日,V5 OF 5,pp.1-5
Attorney, Agent or Firm:
Kenji Yoshida
Jun Ishida