Title:
How to lay an electric circuit element under a multilayer electronic equipment assembly and the three-dimensional module
Document Type and Number:
Japanese Patent JP6257047
Kind Code:
B2
Abstract:
A multilayer electronics assembly and associated method of manufacture are provided. The multilayer electronics assembly includes a plurality of stacked substrate layers. Each of the substrate layers is fusion bonded to at least an adjacent one of the plurality of substrate layers. A first discrete electrical circuit component is bonded to a first layer of the plurality of layers. A bonding material is interposed between the discrete electrical circuit component and the first layer. The bonding material has a reflow temperature at which the bonding material becomes flowable that is higher than a fusion bonding temperature of the substrate layers.
Inventors:
Parker, Ernest, Clyde
Lauriello, Philip, Joseph
Lauriello, Philip, Joseph
Application Number:
JP2014556629A
Publication Date:
January 10, 2018
Filing Date:
February 06, 2013
Export Citation:
Assignee:
Crane Electronics, Incorporated
International Classes:
H01L25/065; H01L25/07; H01L25/18; H05K3/36
Domestic Patent References:
| JP2007324419A | ||||
| JP2008244191A | ||||
| JP2004058088A | ||||
| JP2011228631A | ||||
| JP2002270731A | ||||
| JP2001024333A | ||||
| JP7307574A |
Foreign References:
| WO2011016555A1 | ||||
| WO2011125354A1 |
Attorney, Agent or Firm:
Longhua International Patent Service Corporation