Title:
位相同期ループ回路分周比の設定方法
Document Type and Number:
Japanese Patent JP4672584
Kind Code:
B2
Abstract:
A system and method for configuring a phased-lock loop (PLL) dividing ratio which does not require the phased-lock loop circuit to lock. In one embodiment, the method includes inducing a substantially minimum or a substantially maximum frequency output from a voltage-controlled oscillator (VCO), and configuring a divider with a corresponding dividing ratio. The method may include grounding an input voltage to the VCO. Alternately, the method may include manipulating inputs to a charge pump providing input to the VCO. The charge pump inputs may be manipulated directly or through a phase-frequency detector providing input to the charge pump and adapted to receive additional input signals.
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Inventors:
Kazuhiko Miki
Application Number:
JP2006085784A
Publication Date:
April 20, 2011
Filing Date:
March 27, 2006
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H03K23/64; H03L7/08; H04L7/033
Domestic Patent References:
| JP63226116A | ||||
| JP2001135038A | ||||
| JP2001084709A | ||||
| JP10271001A |
Attorney, Agent or Firm:
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto