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Title:
HYBRID INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS5685845
Kind Code:
A
Abstract:

PURPOSE: To readily trim the upper layer resistance of a hybrid integrated circuit without controlling he depth of the laser trim by providing two layers of resistors on a ceramic substrate.

CONSTITUTION: A lower conductor 10 is formed on the upper surface of a ceramic substrate 100, and a lower layer resistor 20 is formed between the conductors 10. Soldered portion is removed, an insulating layer 30 is formed, and an upper layer resistor 21 is superposed thereon. The superposed portion between the resistors 21 and 22 is set less than the half of the length l or of the width W. The maximum irregularity of ordinary resistance values falls within approx. ±30%, and it is sufficient to control it with the laser trim less than 1/2 of the L or W. If the irregularity falls within ± several percentage, the area of the superposed area of the resistance layers can be correspondingly increased. An IC cap 40 or a container 41 and so forth are mounted on the substrate 100 trimmed with a laser, thereby forming a hybrid IC. This configuration can eliminate entirely such operations as the control of the depth of the laser trim and the prevention of the removal of the lower layer and can provide an easy trimming operation.


Inventors:
NAKAZAWA TERUMI
Application Number:
JP16146279A
Publication Date:
July 13, 1981
Filing Date:
December 14, 1979
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01C17/242; H01C17/24; H01L21/822; H01L27/01; H01L27/04; H01L27/06; H05K3/46; (IPC1-7): H01C17/24; H01L27/01



 
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