Title:
Hybrid transformer structure on a semiconductor device
Document Type and Number:
Japanese Patent JP6247308
Kind Code:
B2
Abstract:
Several novel features pertain to a hybrid transformer formed within a semiconductor die having multiple layers. The hybrid transformer includes a first set of windings positioned on a first layer of the die. The first layer is positioned above a substrate of the die. The first set of windings includes a first port and a second port. The first set of windings is arranged to operate as a first inductor. The hybrid transformer includes a second set of windings positioned on a second layer of the die. The second layer is positioned above the substrate. The second set of windings includes a third port, a fourth port and a fifth port. The second set of windings is arranged to operate as a second inductor and a third inductor. The first set of windings and the second set of windings are arranged to operate as a vertical coupling hybrid transformer.
Inventors:
Chi Shun Lo
Jae Shun Ran
Mario Francisco Verez
Junghae Kim
Jae Shun Ran
Mario Francisco Verez
Junghae Kim
Application Number:
JP2015543162A
Publication Date:
December 13, 2017
Filing Date:
November 21, 2013
Export Citation:
Assignee:
Qualcomm, Inc.
International Classes:
H01F19/06; H01F17/00; H01L21/822; H01L27/04
Domestic Patent References:
| JP8148354A | ||||
| JP2005223261A | ||||
| JP2009071045A | ||||
| JP2004235584A |
Foreign References:
| US20070247269 |
Attorney, Agent or Firm:
Yasuhiko Murayama
Kuroda Shinpei
Kuroda Shinpei