Title:
ヒステリシスコンパレータ回路
Document Type and Number:
Japanese Patent JP4211616
Kind Code:
B2
Abstract:
An input voltage is applied to an inverting input terminal of a comparator having no hysteresis. A first constant voltage is divided by resistors to create a reference voltage. The reference voltage is applied to a non-inverting input terminal of the comparator through a resistor. Only while an output voltage of the comparator is a low level, a predetermined constant current is supplied to a supply point of the reference voltage and a constant current of the same magnitude is absorbed from the non-inverting input terminal of the comparator.
Inventors:
Kamei Toshishige
Application Number:
JP2004018393A
Publication Date:
January 21, 2009
Filing Date:
January 27, 2004
Export Citation:
Assignee:
株式会社デンソー
International Classes:
H03K5/08; H03K3/0233; H03K5/153
Domestic Patent References:
| JP399513A | ||||
| JP10197572A | ||||
| JP1300708A |
Attorney, Agent or Firm:
Takashi Ito
Takanori Kubo
Akira Nagai
Hirohiko Usui
Takanori Kubo
Akira Nagai
Hirohiko Usui
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