Title:
【発明の名称】グリッチの生じないクロックイネーブル回路
Document Type and Number:
Japanese Patent JPH11506885
Kind Code:
A
Abstract:
A circuit utilizes a toggle flip-flop, a D flip-flop and combinatorial logic to generate a clock signal which can be enabled or disabled without creating spikes or shortened pulses in the clock signal. The circuit receives an input clock signal and an input clock enable signal. The circuit generates an output clock signal which is an enabled/disabled version of the input clock signal, controlled by the input clock enable signal. The circuit thus provides the operational advantages of enabling or disabling, with a single control signal, groups of logic circuits triggered by a common clock signal.
Inventors:
Mote, El Randall Jr.
Application Number:
JP50112497A
Publication Date:
June 15, 1999
Filing Date:
June 06, 1996
Export Citation:
Assignee:
Samsung Electronics Company Limited
International Classes:
G06F1/04; G06F1/10; H03K19/096; H03K3/02; H03K5/1252; H03K5/156; (IPC1-7): H03K3/02; H03K5/1252
Attorney, Agent or Firm:
Aoyama Ryo (2 outside people)