Title:
【発明の名称】クロック再生回路および時間軸誤差補正装置
Document Type and Number:
Japanese Patent JP2776098
Kind Code:
B2
Abstract:
In a clock generator circuit, a zero hold circuit produces from a fixed clock signal a zero hold clock signal which is in phase with an external sync signal. A phase comparator circuit produces phase difference data indicating the phase difference between the external sync signal and an internal sync signal. A counter cleared by the external sync signal counts pulses of the zero hold clock signal to obtain count data. A memory receiving the phase difference data and the count data as its address input produces the internal sync signal when the count data is smaller than the number of pulses in one cycle of the external sync signal having no time-base variations, and a phase control signal determined by the phase difference data and the count data. A phase shifter shifts the phase of the zero hold clock according to the phase control signal to obtain a modified clock signal synchronized with the external sync signal.
Inventors:
FURUMYA SHIGERU
TAKEMURA YOSHA
TAKEMURA YOSHA
Application Number:
JP31209291A
Publication Date:
July 16, 1998
Filing Date:
November 27, 1991
Export Citation:
Assignee:
MATSUSHITA DENKI SANGYO KK
International Classes:
H04L7/033; H04N5/06; H04N5/932; H04N5/945; H04N5/956; (IPC1-7): H04N5/956; H04L7/033; H04N5/06
Domestic Patent References:
| JP62110382A |
Attorney, Agent or Firm:
Tomoyuki Takimoto (1 person outside)