Title:
【発明の名称】テスト機能付きカウンタ装置
Document Type and Number:
Japanese Patent JP2872098
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To eliminate a load cycle for writing from an external test pattern generation circuit and shorten the testing time by generating and writing test data during test mode operation between a storage element and an operational circuit inside a counter by the number of clocks equivalent to that during normal operation. SOLUTION: A data which is held by a latch circuit 2 (i-1) of a bit element i-1A (i=0 to 7) is transfered to a latch circuit 1 (i-1), and an operational circuit 80 (i-1) operates between the data held by the circuit 2 and a data held by a latch circuit 21i of upper bit element n at that time. Through this operation, a test data is generated to overflow or underflow the data held in the latch circuit li of lower bit element iA of bit element (i-1) from the data held in the latch circuit 2i. Therefore, the test data generated from the latch circuit 21i is written in the latch circuit li. Thus, it becomes unnecessary to write a test data for function test from an external test data generation circuit to a counter.
Inventors:
TOZAWA KAZUO
Application Number:
JP1407296A
Publication Date:
March 17, 1999
Filing Date:
January 30, 1996
Export Citation:
Assignee:
NIPPON DENKI AISHII MAIKON SHISUTEMU KK
International Classes:
G01R31/28; H03K21/40; G01R31/26; (IPC1-7): G01R31/28; G01R31/26; H03K21/40
Domestic Patent References:
| JP396013A | ||||
| JP4183115A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)