PURPOSE: To more remarkably improve a sampling speed than a conventional speed, while holding the quality of an analog input signal.

CONSTITUTION: A CCD array 20a has a set 21a of a capture cell. The set 21a of the capture cell is constituted of plural CMOS transistor Q1A-QNA, and first charge transfer cells 23a.1-23a.N to which these transistors are connected, respectively. When a delay line with a tap supplies successively a sampling signal to each of plural capture cells, the corresponding CMOS transistor conducts and a first charge transfer cell 23 samples the data of an analog input signal. When a first charge transfer cell 23 becomes full of data, the data is transferred along a train of many charge transfer cells 24 connected in series to each first charge transfer cell 23 in accordance with clocks P1-/P1 of different phases.