Title:
【発明の名称】EFM信号のフレーム周期検出回路及びEFM信号再生用ビット同期クロック信号の周波数制御方法
Document Type and Number:
Japanese Patent JP2972657
Kind Code:
B2
Abstract:
A system for controlling the frequency of a bit synchronizing clock signal used for reproducing an EFM signal, comprises an EFM signal frame period detecting circuit for frequency-dividing an EFM signal by 117 to output a +E,fra 1/117+EE frequency-divided signal as a frame period signal. A control unit counts the level transition interval of the EFM signal by the bit synchronizing clock signal, selects a maximum count value in a detecting duration defined by each frame period signal, and compares the maximum count value with a predetermined value corresponding to the bit length of a frame synchronizing signal included in the EFM signal. When the maximum count value is larger than the predetermined value, the control unit controls to decrease the oscillation frequency of a bit synchronizing clock signal generating circuit, and when the maximum count value is larger than the predetermined value, the control unit controls to increase the oscillation frequency of a bit synchronizing clock signal generating circuit, with the result that the frequency of the bit synchronizing clock signal is controlled to maintain the counted pulse width of the frame synchronizing signal equal to the length of 11 bit synchronizing clock signals.
Inventors:
CHIBA TOSHISHIGE
NOGAWA HIROMICHI
NOGAWA HIROMICHI
Application Number:
JP16420397A
Publication Date:
November 08, 1999
Filing Date:
June 20, 1997
Export Citation:
Assignee:
YAMAGATA NIPPON DENKI KK
International Classes:
G11B20/14; G11B27/30; H03M5/14; H04L7/02; H04L7/08; H04L25/40; H04L25/49; (IPC1-7): G11B20/14; H03M5/14
Domestic Patent References:
| JP9284127A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)