Title:
【発明の名称】MOS電界効果トランジスタ及びその製造方法
Document Type and Number:
Japanese Patent JP2932429
Kind Code:
B2
Abstract:
A manufacturing method of high voltage MOSFET includes a process forming the first and second conductive wells in a semiconductor substrate; process forming drift areas in the first and second conductive wells; process growing an isolation membrane on the substrate surface between the first and second conductive wells; process forming a gate insulation film; process forming a gate on the gate insulation film above the first and second conductive wells; process forming low concentration n-and p-type dopant areas in the drift areas of the parts adjacent to the gate; process forming buried diffusion areas in the first and second conductive wells; process forming source/drain having a body contact on a side on the buried diffusion areas in the first and second conductive wells; process forming an insulation film having a contact formed in such way that is exposed the surface of source/drain on the entire surface of the substrate including the gate and isolation membrane; process forming a metal film on the insulation film; and process forming source/drain electrodes and the metal field plates, by etching the metal film using a mask.
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Inventors:
OOKYON KUON
FUUNNHO JEON
FUUNNHO JEON
Application Number:
JP32162596A
Publication Date:
August 09, 1999
Filing Date:
December 02, 1996
Export Citation:
Assignee:
ERU JII SEMIKON CO LTD
International Classes:
H01L21/336; H01L21/8238; H01L27/092; H01L29/06; H01L29/10; H01L29/40; H01L29/78; (IPC1-7): H01L29/78; H01L21/8238; H01L27/092
Domestic Patent References:
| JP750413A | ||||
| JP58137256A |
Attorney, Agent or Firm:
Fumio Sasashima (1 person outside)