Title:
【発明の名称】制御されたディバイダパルス幅を用いたPLL周波数シンセサイザ
Document Type and Number:
Japanese Patent JP2003519951
Kind Code:
A
Abstract:
A method and an apparatus relating to a PLL circuit for frequency synthesizer applications. By using a composite PFD large and small phase variations between a reference signal and the divider output are compensated for. The composite phase frequency detector (PFD) has both a digital phase frequency detector (digital PFD) and an analog phase detector (analog PD) with the digital PFD compensating for large phase differences and the analog PD compensating for smaller phase differences. The PLL automatically chooses between these two components in the composite PFD by controlling the pulse width of the divider output. This is accomplished by synchronizing the dead zone of the digital PFD with the active pulse width of the divider output and by similarly synchronizing the phase detector window of the analog PD to be within both the dead zone of the digital PFD and the active pulse width of the divider output. Thus, during the active pulse of the divider output, the analog PD is operative while during the inactive pulse the digital PFD is operative. By essentially having only one PD active at any time, problems with analog/digital mixed circuits are avoided.
Inventors:
Lily, Thomas, A.D.
Application Number:
JP2001550878A
Publication Date:
June 24, 2003
Filing Date:
January 05, 2001
Export Citation:
Assignee:
Connexant Systems, Inc.
International Classes:
H03K21/10; H03K23/66; H03L7/087; H03L7/113; H03L7/18; H03L7/183; H03L7/197; H03L7/089; (IPC1-7): H03L7/113; H03L7/087; H03L7/183; H03L7/197
Attorney, Agent or Firm:
Sanshin Iwao (2 people outside)