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Title:
WIRING SYSTEM FOR SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH0774606
Kind Code:
A
Abstract:

PURPOSE: To reduce the current consumption by connecting a terminal resistance to a transmission line for suppression of reflection only when the signal level varies on the transmission line.

CONSTITUTION: The signal level of an input/output circuit 5 of a DRAM chip 2 is decided by the exclusive power supply VHO1 and VOL1. These VOH1 and VOL1 can be applied from outside of the chip 2 and also can be generated in the chip 2. Under such conditions, a termination circuit 1 is set at the resistance value equal to the characteristic impedance of a transmission line 4 only when output 01 received from the circuit 5 is changed and otherwise set at a high resistance level. As a result, a current flows to the circuit 1 from a terminal power voltage VTT only in a signal transition state and no current flows to the circuit 1 in other periods. Thus the current consumption can be reduced.


Inventors:
KAWAHARA TAKAYUKI
ETO JUN
NAKAGOME YOSHINOBU
AOKI MASAKAZU
Application Number:
JP17920793A
Publication Date:
March 17, 1995
Filing Date:
July 20, 1993
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H03K17/76; G06F12/00; G06F13/16; G11C11/401; H03K19/0175; H03M5/02; (IPC1-7): H03K17/76; H03K19/0175; H03M5/02
Attorney, Agent or Firm:
Masatoshi Isomura