PURPOSE: To prevent a pipeline from being emptied until an instruction is loaded from an instruction cached into a main storage device.

CONSTITUTION: The leading address of an exceptional processing routine is stored in a result register 116, and in a succeeding cycle, the leading address is transferred to an instruction pointer 102 to start an instruction cache 104. A finite status logic 111 goes to the succeeding step independently of the existence of the address of the pointer 102 in the cache 104. Even when a cache miss is generated, the data transfer of the cache 104 to/from the main storage device can be overlapped to the succeeding step of the logic 111, so that a required instruction can be prevented from being queued due to the generation of a miss in the cache 104.