Title:
【発明の名称】デジタル映像デコーダのための二段階同期化方式
Document Type and Number:
Japanese Patent JPH08505513
Kind Code:
A
Abstract:
A novel synchronization scheme for use in connection with digital signal video decoder comprises a pre-parser, a channel buffer, and a post-parser. The pre-parser synchronizes to a multiplexed system bitstream received from a fixed rate channel. The video bitstream component of a multiplexed system bitstream is then extracted and synchronized prior to being transferred bit-serially from the pre-parser to a channel buffer. The post-parser is coupled to the channel buffer and to a video decoder in a series configuration. The post-parser separates the various layers of video data from the video bitstream component. The post-parser performs a translation operation on the video bitstream component and converts the bitstream data into symbol data. The symbol data is subsequently processed by the video decoder so as to reconstruct an originally encoded picture or frame. Preferably, the multiplexed system bitstream data structure conforms to some format agreed upon among video digital businesses involved in transmission and reception. In accordance with one aspect of the present invention, the pre-parser and the post-parser operate independent of each other, and operate at different processing rates.
Inventors:
Old, David Earl
Application Number:
JP51270795A
Publication Date:
June 11, 1996
Filing Date:
October 18, 1994
Export Citation:
Assignee:
LSI Logic Corporation
International Classes:
H04N11/04; H03M7/00; H04N7/08; H04N7/081; H04N7/26; H04N7/50; (IPC1-7): H04N7/08; H04N7/081; H04N7/24; H04N11/04
Attorney, Agent or Firm:
Kyozo Yuasa (6 people outside)