Title:
LEVEL CONVERSION CIRCUIT
Document Type and Number:
Japanese Patent JPH0669781
Kind Code:
A
Abstract:
PURPOSE: To provide a level conversion circuit which quickly operates by low power consumption.
CONSTITUTION: The logical threshold voltage of a second CMOS inverters MP 12 and 13 is made lower than that of a first CMOS inverters MP11 and MN11 and the current of current control circuits MP13 to MP16 provided with an input signal VIN. the output of the second CMOS inverter, reference voltage Vbb for discrimination, etc., is provided for a current mirror circuit MN12. When the signal level of the input signal VIN is satisfactorily lowered, the current of the current control circuits and the current mirror circuit is interrupted to attain the operation by low power consumption. Thus, a signal in a TTL level is converted into a CMOS level.
Inventors:
HIGUCHI HISAYUKI
TACHIBANA MASARU
SUZUKI MAKOTO
SASAKI TOSHIO
HONMA NORIYUKI
TACHIBANA MASARU
SUZUKI MAKOTO
SASAKI TOSHIO
HONMA NORIYUKI
Application Number:
JP28597091A
Publication Date:
March 11, 1994
Filing Date:
October 31, 1991
Export Citation:
Assignee:
HITACHI LTD
International Classes:
H03K5/02; H03K19/0185; (IPC1-7): H03K19/0185; H03K5/02
Attorney, Agent or Firm:
Ogawa Katsuo
Next Patent: BI-MIS LOGICAL CIRCUIT