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Title:
SEMICONDUCTOR TEST PATTERN, FORMING METHOD AND USING METHOD THEREOF
Document Type and Number:
Japanese Patent JPH07122610
Kind Code:
A
Abstract:

PURPOSE: To facilitate the determination of contact between an isolation layer and a substrate and the positional shift of a buried layer by forming a P-type diffusion test layer in parallel with an N-type buried layer and an N-type diffusion test layer formed sequentially on a P-type substrate.

CONSTITUTION: An N--type epitaxial layer 9 and an N-type buried test layer 10 are formed on a P-type substrate 8 and an N+-type diffusion test layer 13 is formed on the surface of the N--type epitaxial layer 9. At least one P-type diffusion test layer 11 is then formed using a surface position of the N--type epitaxial layer 9 spaced apart horizontally, by a predetermined distance, from the design position of the N-type buried test layer 10 as a design position. Thereafter, a semiconductor test pattern comprising an electrode 14 connected with the N+-type test layer 13 and an electrode 12 connected with the P-type diffusion test layer 11 is formed in the wafer simultaneously with the main pattern of a PN junction isolation bipolar transistor. A decision can be made easily whether the P-type isolation layer of main pattern reached the P-type substrate 1 by checking conduction between the electrode 12 and the rear electrode 16.


Inventors:
OGIWARA ATSUSHI
Application Number:
JP26684893A
Publication Date:
May 12, 1995
Filing Date:
October 26, 1993
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC WORKS LTD
International Classes:
G01R31/28; H01L21/331; H01L21/66; H01L21/761; H01L29/73; H01L29/732; (IPC1-7): H01L21/66; G01R31/28; H01L21/331; H01L21/761; H01L29/73
Attorney, Agent or Firm:
Shigeji Sato (1 person outside)