Title:
【発明の名称】シンクロノスディラムのリフレッシュカウンターテストモード方法及びその装置
Document Type and Number:
Japanese Patent JP2985834
Kind Code:
B2
Abstract:
A refresh counter for an SDRAM and a method of testing the same. An internal bank select address for the test of the refresh counter has a predetermined state in a test mode to correspond to an external bank select address in a burst mode, so that the refresh counter can simply be tested in the test mode. The refresh counter comprises a first counter circuit for outputting a least significant bit as the internal bank select address in the test mode in response to an address signal and a reset pulse signal. The address signal is generated in each automatic refresh cycle, and the reset pulse signal is generated when the present mode is set to the test mode by a mode register set command. The refresh counter further comprises n second counter circuits connected in series to the first counter circuit, for outputting n bits of a row address.
More Like This:
| JPH0276196 | SEMICONDUCTOR DEVICE |
| JPH05198165 | DYNAMIC RAM |
Inventors:
GO SHOKUN
Application Number:
JP15737297A
Publication Date:
December 06, 1999
Filing Date:
June 02, 1997
Export Citation:
Assignee:
GENDAI DENSHI SANGYO KK
International Classes:
G11C11/407; G11C11/401; G11C11/406; G11C29/02; G11C29/08; (IPC1-7): G11C11/401; G11C11/406; G11C11/407; G11C29/00
Domestic Patent References:
| JP6333391A |
Attorney, Agent or Firm:
Keiichi Yamamoto