Title:
IC PARALLEL TEST SYSTEM
Document Type and Number:
Japanese Patent JP3232588
Kind Code:
B2
Abstract:
PURPOSE: To shorten the time of a test by a method wherein the ratio of IC's under test as objects to be tested to IC's under test as objects not to be tested is checked and a function to automatically judge whether a testing flow is continued or not is provided.
CONSTITUTION: Regarding a plurality of IC's 6a to 6n under test which are tested in parallel, the test and judgement result of the individual IC's 6a to 6n under test with reference to individual test items is obtained. Regarding the IC's which have been judged to be defective in the course of a testing flow, their test with reference to a next test item is not performed. The IC's which have been judged to be good with reference to all the test items after their final test item has been finished are judged to be good IC's. The IC's which have been judged to be detective in their halfway test item are judged to be defective IC's. At this time, their yield check inside their parallel test which compares and judges a judgment result is checked with reference to a reference value, regarding the ratio of the number of good IC's under test to the number of defective IC's by means of the test and judgment result, which has been preset for the test; a yield, regarding their test items, which judges whether the testing flow is to be continued or not on the basis of the check is monitored.
Inventors:
Takashi Sebata
Application Number:
JP18283891A
Publication Date:
November 26, 2001
Filing Date:
July 24, 1991
Export Citation:
Assignee:
NEC
International Classes:
G01R31/26; H01L21/66; H01L21/822; H01L27/04; B07C5/36; (IPC1-7): H01L21/66; B07C5/36; G01R31/26; H01L21/822; H01L27/04
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Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)