To provide an IC test device which can easily analyze defect by correcting the number of output stages by adjusting to latency setting for every pin of memories to be tested, and its control method and a storage medium.

The IC test device 1 provided with a sampling circuit 6a outputting comparison data J being an object of comparison when the normal/ defective condition of a memory W to be tested is discriminated, a latency circuit 6b outputting discrimination data K being the discrimination standard of the normal/defective condition of the memory W to be tested by conforming to the phase of the comparison data J outputted by the sampling circuit 6a, a logic comparator circuit 6c for comparing logic of the comparison data J with discrimination data K and outputting discriminated result data H, is provided with a latency compensating circuit 6d outputting the discriminated result data H outputted from the logic comparator circuit 6c by conforming to the phase of an address pattern I specifying an address in the memory W to be tested.