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Patent Searching and Data


Title:
IC TESTER ADDING/SUBTRACTING OFFSET VOLTAGE
Document Type and Number:
Japanese Patent JPH05281301
Kind Code:
A
Abstract:

PURPOSE: To reduce the occurrence of errors generated depending upon the dynamic range of a voltage measuring instrument by adding an offset voltage and signal voltage to a DUT and eliminating the offset voltage from the output voltage of the DUT.

CONSTITUTION: An L-power source 2A generates an L-voltage and an H-power source 2B generates an H-voltage. An offset power source 2C generates an offset voltage. Offset adder circuits 3A and 3B respectively add the offset voltage to the L- and H-voltages. Offset elimination circuits 4A and 4B add the outputs of the circuits 3A and 3B to a DUT 10 by using patterns from a pattern generator 1B and subtract the offset voltage from the output of the DUT 10. Voltage measuring instruments 5A and 5B measure the outputs of the circuits 4A and 4B.


Inventors:
Masao Yamamoto
Application Number:
JP10369192A
Publication Date:
October 29, 1993
Filing Date:
March 30, 1992
Export Citation:
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Assignee:
Ando Electric Co., Ltd.
International Classes:
G01R31/28; G01R31/319; G01R31/26; (IPC1-7): G01R31/28; G01R31/26