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Patent Searching and Data


Title:
IIR FILTER CIRCUIT
Document Type and Number:
Japanese Patent JPH08111866
Kind Code:
A
Abstract:

PURPOSE: To reduce the cost by processing a time base IIR filter in the 2-screen transmission system with one filter circuit so as to reduce the circuit scale.

CONSTITUTION: A multiplexer circuit 1 multiplexes image data a, b alternately for each image frame to obtain multiplexed data (c). A subtracter circuit 2 obtains a difference between the multiplexed data (c) and delay data (e) to obtain a difference (d). A coefficient arithmetic circuit 3 multiplies a circuit selected by a coefficient selection signal (f) with the difference data (d) to be received and gives the result to an adder circuit 4. The adder circuit 4 adds the delay data (e) to output data from the coefficient arithmetic circuit 3 to obtain local decoding data (g). The obtained local decoding data (g) are fed to a 2-frame delay circuit 5 and fed to an output terminal 8.


Inventors:
SUZUKI TOSHINAKA
Application Number:
JP24762894A
Publication Date:
April 30, 1996
Filing Date:
October 13, 1994
Export Citation:
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Assignee:
NIPPON ELECTRIC ENG
International Classes:
H04N19/117; H03H17/04; H04N7/24; H04N19/00; H04N19/146; H04N19/42; H04N19/423; H04N19/503; H04N19/80; (IPC1-7): H04N7/24; H03H17/04
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)